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DFT Design Engineer

The Programme 



  • Block, IP and VLSI top level DFT implementation (MBIST, Scan, Boundary Scan, analog/IP and RF test etc.), SoC database DFT coding and integration 
  • Participate in SoC test spec/plan definition, complete DFT design document and signoff review checklists 
  • SoC DFT quality sign-off; DFT SDC and FV constraint generation and release; ECO and formal check 
  • Test patterns/vectors generation and verification, including RTL level, pre&post layout gate level simulation 
  • Co-work with implementation and backend team on physical design and timing closure
  • Co-work with test engineer on ATE patterns bring-up, debugging, failure analysis and yield improvement. 

Required Skills and Abilities 

  • Good Knowledge of DFT technology and RTL/netlist integration flow, including MBIST, DC/AC-Scan, ATPG, JTAG&iJTAG, IP test logic design,and test pattern verification 
  • Expertise with various kinds of DFT tools including Tessent-shell, DFTC,TestKompress, TetraMax etc 
  • Good Knowledge of digital ASIC design; experience in Verilog/VHDL coding and simulation debugging 
  • Experience in Synthesis, STA and formality check will be plus 
  • Proficient in Perl, tcl and shell script 
  • BSEE degree or above 
  • Good team work spirit 
Closed 3 months ago
Closed 3 months ago
  • Job type:Graduate Jobs
  • Disciplines:

    Engineering, Telecommunications

  • Citizenships:

  • Locations:


  • Closing Date:31st Mar 2022, 6:00 pm


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