Employer Navigation

Chip Front-end Design Engineer profile banner profile banner

Chip Front-end Design Engineer

The Programme 

台积公司成立于1987年,率先开创了专业集成电路制造服务之商业模式,自此成为全球规模专业集成电路制造服务公司。台积公司以领先业界的制程技术及设计解决方案组合支持其客户及伙伴生态系统的蓬勃发展,以此释放全球半导体产业的创新。身为全球的企业公民,台积公司的营运范围遍及亚洲、欧洲及北美,致力成为企业社会责任的行动者。 

Responsibilities 

  • RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips. 
  • Design flow/methodology development and innovation for front-end design challenges.
  • Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips. 

Required Skills and Abilities 

  • MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus. 
  • New graduate or 3+ years working experience. 
  • Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows. 
  • Familiar with tcl/Perl/Python program. 
     
     
     
Closed 6 days ago
Closed 6 days ago
  • Job type:Graduate Jobs
  • Disciplines:

    Computer Science, Engineering Electrical

  • Citizenships:

  • Locations:

    Nanjing

  • Closing Date:8th May 2021, 6:00 pm

Search

Enter an employer or university you want to find in our search bar.