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IC Sign off Engineer

The Programme 

台积公司成立于1987年,率先开创了专业集成电路制造服务之商业模式,自此成为全球规模专业集成电路制造服务公司。台积公司以领先业界的制程技术及设计解决方案组合支持其客户及伙伴生态系统的蓬勃发展,以此释放全球半导体产业的创新。身为全球的企业公民,台积公司的营运范围遍及亚洲、欧洲及北美,致力成为企业社会责任的行动者。 

Responsibilities 

  • Responsible for checking the advanced chip function before fabrication. Given the verification, the chip can exhibit expecting high performance after fabrication 
  • Reliable flow setting, identify violation root cause, and provide the fixing strategy to achieve high quality chips. 
  • Professional at one domain of blow knowledge at least. Signoff team not only executes the advanced signoff skill, but also push the boundary of flow to reach higher quality and productivity. 
  • STA (static timing analysis): using commercial timing signoff EDA tool combining advanced on-chip timing analysis method (OCV) to achieve timing closure before tape-out. 
  • IR analysis: define the reasonable IR drop spec, and explore the opportunity to realize the function with sufficient voltage support and reasonable power consumption. 
  • PV (physical verification): verify and achieve the chip without DRC (design rule check) and LVS (layout versus schematic).
  • With the verification, the following fabrication can minimize the defect and reach high yield performance. 

Required Skills and Abilities 

  • MS degree or above in EE, CS, Physics or related domains. Experience in Digital IC design flow, especially signoff, is a plus 
    Innovative, persistence and flexible personality. 
  • For frequent cross team cooperation and customer support, excellent communication/presentation skill 
  • Excellent English skill, CET6 
  • Software skill, ex: tcl, python 
Closed 4 months ago
Closed 4 months ago
  • Job type:Graduate Jobs
  • Disciplines:

    Computer Science, Engineering Electrical

  • Citizenships:

  • Locations:

    Nanjing

  • Closing Date:8th May 2021, 6:00 pm

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