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Layout Engineer

The Programme 



  • Full layout design for std cell/IO/SRAM IPs in advanced node 
  • Work on the physical verification(DRC/LVS/Antenna ...) 
  • Work on test chip layout design and verification
  • Close cooperation with designers on PPA optimization  

Required Skills and Abilities 

  • At least BS Degree of Microelectronics or Physics 
  • Excellent graduate or at least 1 years' related working experience 
  • Familiar with layout design and verification tools(Virtuoso,Laker,Calibre) 
  • Familiar with design rule and layout effect in advanced process. 
  • Excellent skills of communication and teamwork are also expected. 
  • Programming experience(perl/tcl skill) will be a plus. 
  • Experience in advanced process (n16 and beyond) will be a plus. 
Closed 4 months ago
Closed 4 months ago
  • Job type:Graduate Jobs
  • Disciplines:


  • Citizenships:

  • Locations:


  • Closing Date:8th May 2021, 6:00 pm


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